1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising an epitaxially grown silicon/germanium mixture in the active regions of the transistors.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit elements in complex integrated circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits, wherein performance of the transistors in the speed critical signal paths substantially determines overall performance of the integrated circuit. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface positioned between highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Upon continuously reducing the channel length of field effect transistors, generally, an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high speed transistor elements, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, other alternatives have been developed in increasing the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors. One promising approach in this respect is the generation of a certain type of strain in the channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. For example, for a standard crystallographic configuration of the silicon-based channel region, a compressive strain component in a P-channel transistor may result in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors. The desired compressive strain component may be obtained according to well-established approaches by incorporating a strain-inducing semiconductor material, for instance in the form of a silicon/germanium mixture or alloy, in the active region of the P-channel transistor. For example, after forming the gate electrode structure, corresponding cavities may be formed laterally adjacent to the gate electrode structure in the active region and may be refilled with the silicon/germanium alloy which, when grown on the silicon material, may have an internal strained state, which in turn may induce a corresponding compressive strain component in the adjacent channel region. Consequently, a plurality of process strategies have been developed in the past in order to incorporate a highly strained silicon/germanium material in the drain and source areas of P-channel transistors.
In other approaches, the inferior controllability of the channel region of the short channel transistors caused by the continuous reduction of the critical dimensions of gate electrode structures has been addressed by an appropriate adaptation of the material composition of the gate dielectric material. To this end, it has been proposed that, for a physically appropriate thickness of a gate dielectric material, i.e., for reducing the gate leakage currents, a desired high capacitive coupling may be achieved by using appropriate material systems, which have a significantly higher dielectric constant compared to the conventionally used silicon dioxide-based materials. For example, dielectric materials including hafnium, zirconium, aluminum and the like may have a significantly higher dielectric constant and are, therefore, referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher when measured in accordance with typical measurement techniques. As is well known, the electronic characteristics of the transistors also strongly depend on the work function of the gate electrode material, which in turn influences the band structure of the semiconductor material in the channel regions separated from the gate electrode material by the gate dielectric layer. In well-established polysilicon/silicon dioxide-based gate electrode structures, the corresponding threshold voltage, that is strongly influenced by the gate dielectric material and the adjacent electrode material, is adjusted by appropriately doping the polysilicon material in order to appropriately adjust the work function of the polysilicon material at the interface between the gate dielectric material and the electrode material. Similarly, in gate electrode structures including a high-k gate dielectric material, the work function has to be appropriately adjusted for N-channel transistors and P-channel transistors, respectively, which may require appropriately selected work function adjusting metal species, such as lanthanum for N-channel transistors and aluminum for P-channel transistors and the like. For this reason, corresponding metal-containing conductive materials may be positioned close to the high-k gate dielectric material in order to form an appropriately designed interface that results in the target work function of the gate electrode structure. In some conventional approaches, the work function adjustment is performed at a very late manufacturing stage, i.e., after any high temperature processes, after which a placeholder material of the gate electrode structures, such as polysilicon, is replaced by an appropriate work function adjusting species in combination with an electrode metal, such as aluminum and the like. In this case, however, very complex patterning and deposition process sequences are required in the context of gate electrode structures having critical dimensions of 50 nm and significantly less, which may result in severe variations of the resulting transistor characteristics.
Therefore, other process strategies have been proposed in which the work function adjusting materials may be applied in an early manufacturing stage, i.e., upon forming the gate electrode structures, wherein the metal species may be thermally stabilized and encapsulated in order to obtain the desired work function and thus threshold voltage of the transistors without being unduly influenced by the further processing. It turns out that, for many appropriate metal species and metal-containing electrode materials, an appropriate adaptation of the band gap of the channel semiconductor material may be required, for instance, in the P-channel transistors in order to appropriately set the work function thereof. For this reason, frequently, a so-called threshold adjusting semiconductor material, for instance in the form of a silicon/germanium mixture, is formed on the active regions of the P-channel transistors prior to forming the gate electrode structures, thereby obtaining the desired offset in the band gap of the channel semiconductor material. The electronic characteristics, and in particular the threshold voltage of the P-channel transistors, thus strongly depends on the characteristics of the silicon/germanium mixture, i.e., on the material composition and the layer thickness as well as on the uniformity of these parameters, so that complex selective epitaxial growth techniques are typically required in order to form the silicon/germanium mixture with uniform and predefined characteristics.
Consequently, in sophisticated semiconductor devices, a silicon/germanium material may have to be provided with precisely defined characteristics, for instance, as explained before for appropriately adjusting the band gap offset of the channel material, while, in other cases, additionally or alternatively, a silicon/germanium material may have to be provided as an embedded strain-inducing material, wherein the characteristics of the embedded semiconductor material may strongly affect performance of the transistors. Although these process techniques may provide significant advantages, for instance in view of reducing overall process complexity, for instance in view of replacement gate approaches or in view of enhancing overall performance, it turns out, however, that the material composition and layer thickness of an epitaxially grown silicon/germanium material may not be arbitrarily selected without significantly influencing the finally achieved transistor characteristics, as will be described in more detail with reference to FIGS. 1a-1e. 
FIG. 1 a schematically illustrates a cross-sectional view of a semiconductor device 100 in which a silicon/germanium material is to be provided in the channel area of one type of transistor on the basis of an epitaxial growth process. In the manufacturing stage shown, the device 100 comprises a substrate 101 and a silicon-based semiconductor layer 102, wherein the substrate 101 and the semiconductor layer 102 form a bulk configuration or an SOI (silicon-on-insulator) configuration, depending on the desired transistor architecture. For example, for an SOI configuration, a buried insulating layer (not shown) is formed below the semiconductor layer 102 and thus isolates the layer 102 with respect to the substrate 101. The semiconductor layer 102 further comprises isolation structures 102C, such as shallow trench isolations, which laterally delineate semiconductor regions or active regions, two of which, indicated as 102A, 102B, are illustrated in FIG. 1a. In the example shown, the active region 102A corresponds to the semiconductor region of a P-channel transistor, while the active region 102B corresponds to an N-channel transistor. An appropriate mask layer 103, such as a silicon dioxide material, may be formed on the active region 102B in order to act as a deposition mask for the selective epitaxial growth of a silicon/germanium material in the active region 102A. In some illustrative approaches, typically, a recess 102R is provided in the region 102A prior to actually depositing the silicon/germanium material.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. The isolation structure 102C may be formed by using sophisticated lithography, etch, deposition and planarization techniques, wherein, prior to or after forming the isolation structure 102C, appropriate well dopant species may be incorporated into the active regions 102A, 102B in order to define the basic transistor characteristics. To this end, any well-established implantation techniques and masking regimes may be applied. Thereafter, the mask 103 is formed, for instance by oxidation, deposition and the like, wherein a non-desired portion of the mask material is removed from above the active region 102A, for instance by applying a resist mask and performing any appropriate etch process. Furthermore, as illustrated, the recess 102R may be formed with an appropriate depth so as to obtain a desired surface topography after the deposition of the silicon/germanium material. Next, a selective epitaxial growth process is performed after any cleaning processes and the like in which process parameters are established in such a manner that a significant semiconductor material deposition is substantially restricted to exposed surface areas of the active region 102A, while any pronounced deposition on dielectric surface areas, such as the mask 103 and the isolation structure 102C, is suppressed. To this end, well-established chemical vapor deposition (CVD) techniques with process temperatures in the range of 650-750° C. have been developed on the basis of appropriately selected gas flow rates and process pressure, wherein the fraction of germanium in the silicon/germanium mixture may be set on the basis of controlling the corresponding gas flow rates. As previously explained, the resulting electronic characteristics, in particular the resulting threshold voltage, may significantly depend on the thickness of the silicon/germanium material and the material composition thereof, i.e., the germanium fraction contained therein. For example, a thickness of approximately 8-12 nm and a germanium content of up to twenty five percent may be used in order to obtain the required threshold voltage.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a silicon/germanium mixture or alloy 104 is formed in the active region 102A and thus represents a portion thereof, thereby providing the desired band gap offset, as discussed above. Furthermore, a gate electrode structure 160A of a P-channel transistor 150A is formed on the channel material 104 and may comprise a gate dielectric material 163A and a metal-containing electrode material 162A, followed by a further electrode material 161, such as silicon and the like. Furthermore, the materials 163A, 162A, 161 may be encapsulated by a spacer structure 165, for instance provided in the form of a silicon nitride material and the like, while a cap layer 164 may also be provided, for instance in the form of silicon dioxide, silicon nitride and the like. Similarly, a gate electrode structure 160B of an N-channel transistor 150B may be formed on the active region 102B and may have basically a similar configuration as the gate electrode structure 160A. That is, a gate dielectric material 163B in combination with a metal-containing electrode material 162B and the electrode material 161 may be provided in combination with the spacer structure 165 and the cap layer 164. It should be appreciated that the gate dielectric materials 163A, 163B may have basically the same configuration and may, however, differ in a work function adjusting species that may have been incorporated therein during the previous processing. For example, frequently, appropriate species may be diffused into the gate dielectric material in order to appropriately modify the characteristics thereof in view of achieving a desired overall work function and thus threshold voltage. Moreover, as discussed above, the gate dielectric layers 163A, 163B comprise a high-k dielectric material, such as hafnium oxide and the like, possibly in combination with a thin conventional dielectric material, for instance in the form of silicon oxynitride and the like, in view of superior interface characteristics. The metal-containing electrode materials 162A, 162B may have substantially the same composition or may also differ with respect to a work function adjusting species, depending on the overall process strategy applied for forming the gate electrode structures 160A, 160B.
A typical process flow for forming the semiconductor device 100 as illustrated in FIG. 1b may comprise the following processes. First, the basic material composition of the gate dielectric layers 163A, 163B may be provided, possibly in combination with any work function adjusting metal species and additional cap materials, such as titanium nitride and the like, and any appropriate treatment, such as anneal processes and the like, may be applied in order to adjust the overall characteristics of the gate dielectric materials 163A, 163B. Thereafter, the same or different materials may be deposited for the layers 162A, 162B, followed by the deposition of the material 161, for instance in the form of amorphous or polycrystalline silicon. Moreover, any further material, such as the cap material 164, is provided and the resulting layer stack is patterned on the basis of sophisticated lithography and etch techniques. Thereafter, the spacer structure 165 is formed by any appropriate deposition and etch strategy in order to confine, in particular, the sensitive materials 163A, 163B and 162A, 162B.
Consequently, by means of the channel material 104, an appropriate threshold voltage for the transistor 150A could, in principle, be obtained, wherein, however, significant defects have been observed in the material 104, as indicated by 104A, when the material 104 is provided with a thickness and material composition as specified above. For example, defect values of 200 000 and more defects per cm2 have been identified upon performing corresponding defect etch experiments. However, corresponding defects in the channel region of the transistor 150A may result in significant variation of transistor characteristics or may even result in a non-acceptable transistor performance.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, the transistor 150A comprises the gate electrode structure 160A, possibly with an additional spacer structure 166, which may include the spacer structure 165 (FIG. 1b). The spacer structure 166 may be used for defining the lateral and vertical dopant profile of drain and source regions 152. Similarly, the transistor 150B comprises the gate electrode structure 160B and corresponding drain and source regions 152 which, however, have an inverse conductivity type compared to the regions 152 of the transistor 150A. The transistors 150A, 150B may be formed on the basis of any appropriate process strategy for providing the spacer structure 166 and the drain and source regions 152. Thus, as illustrated, a channel region 151 comprising the silicon/germanium material 104 may have an inferior performance due to the high number of defects 104A, as discussed above. Basically, the defect rate could be reduced, for instance, by reducing the fraction of germanium material in the layer 104 and/or by reducing the thickness thereof which, however, in turn would result in significantly changed threshold voltages, which, however, may not be compatible with the overall design of the transistor 150A.
FIG. 1d schematically illustrates the device 100 according to other conventional strategies in which a strain-inducing silicon/germanium alloy is to be provided in the active region 102A, without affecting the active region 102B. As shown, cavities 105 are formed in the active region 102A laterally adjacent to the gate electrode structure 160A, which may have a similar configuration as previously described with reference to FIGS. 1b and 1c, while, in other cases, as illustrated, a more conventional configuration may be used, for instance in the form of a conventional dielectric material 163 and the like. It should be appreciated that, if desired, sophisticated gate materials may be provided in a later manufacturing stage.
The cavities 105 are typically formed on the basis of well-established plasma assisted etch recipes, possibly in combination with wet chemical etch processes by using the spacer structure 165 and the dielectric cap material 164 as an efficient etch mask. On the other hand, the active region 102B and the gate electrode structure 160B are covered by a spacer layer 165L, possibly in combination with a resist mask (not shown).
FIG. 1e schematically illustrates the semiconductor device 100 after forming a strain-inducing silicon/germanium material 109 in the active region 102A by applying a selective epitaxial growth technique, wherein a germanium concentration of twenty five atomic percent and higher may typically be used. Although the material 109 may represent a very efficient strain source in the active region 102A, it has been observed that also in this case significant crystal damage 109A is generated upon depositing the material 109 and during further processing.
Consequently, also in this case, performance of the corresponding transistor may be reduced and significant device variations may be introduced due to the incorporation of the strain-inducing semiconductor material 109.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.